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a29dl323 series 32m - bit cmos low voltage dual operation flash memory preliminary 4m - byte by 8 - bit (byte mode) / 2m - word by 16 - bi t (word mode) preliminary (may, 2002, version 0.0) 1 amic technology, inc. features n two bank organiz ation enabling simultaneous execution of erase / program and read n bank organization: 2 banks (8 mbits + 24 mbits) n memory organization: - 4,194,304 words x 8 bits (byte mode) - 2,097,152 words x 16 bits (word mode) n sector organization: 71 sectors (8 kbytes / 4 kwords 8 sectors, 64 kbytes / 32 kwords 63 sectors) n 2 types of sector organization - t type: boot sector allocated to the highest address (sec tor) - b type: boot sector allocated to the lowest address (sector) n 3 - state output n automatic program - program suspend / resume n unlock bypass program n automatic erase - chip erase - sector erase (sectors can be combined freely) n erase suspend / resume n p rogram / erase completion detection - detection through data polling and toggle bits - detection through ry/ by pin n sector group protection - any sector group can be protected - any protected sector group can be temporary unprote cted n sectors can be used for boot application n hardware reset and standby using reset pin n automatic sleep mode n boot block sector protect by wp (acc) pin n conforms to common flash memory interface (cfi) n extra one time pr otect sector provided part no. access time (max.) operating supply voltage power supply current (active mode) (max.) standby current (max.) a29dl323 90ns 2.7v~ 3.6v 16ma 30ma 5 a n operating ambient temperature: - 40 to 85c n program / erase time - program: 9.0 s / byte (typ.) 11.0 s / word (typ.) - sector erase: 0.7 s (typ.) n number of program / erase: 1,000,000 times (min.) n package options - 48 - pin tsop (i) or 63 - ball tfbga general description the a29dl323 is a flash memory organized of 33,554,432 bits and 71 sectors. sectors of this memory can be erased at a low voltage (2.7 to 3.6 v) supplied from a single power source, or the contents of the entire chip can be erased. two modes of memory organization, byte mode (4,194,304 words 8 bits) and word mode (2,097,152 words 16 bits), are selectable so that the memory can be programmed in byte or word units. the a29dl323 can be read while its contents are being erased or program med. the memory cell is divided into two banks. while sectors in one bank are being erased or programmed, data can be read from the other bank thanks to the simultaneous execution architecture. the banks are 8 mbits and 24 mbits. this flash memory comes in two types. the t type has a boot sector located at the highest address (sector) and the b type has a boot sector at the lowest address (sector). because the a29dl323 enables the boot sector to be erased, it is ideal for storing a boot program. in additio n, program code that controls the flash memory can be also stored, and the program code can be programmed or erased without the need to load it into ram. eight small sectors for storing parameters are provided, each of which can be erased in 8 kbytes units . once a program or erase command sequence has been executed, an automatic program or automatic erase function internally executes program or erase and verification automatically. because the a29dl323 can be electrically erased or programmed by writing an instruction, data can be reprogrammed on - board after the flash memory has been installed in a system, making it suitable for a wide range of applications.
a29dl323 series preliminary (may, 2002, version 0.0) 2 amic technology, inc. pin configurations n tsop (i) a29 d l323v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a14 a13 a12 a11 a10 a9 a8 a20 we reset nc wp (acc) ry/by a18 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 i/o 2 i/o 10 i/o 3 i/o 11 vcc i/o 4 i/o 12 i/o 5 i/o 13 i/o 6 i/o 14 i/o 7 i/o 15 (a-1) gnd byte a16 a15 a19 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 i/o 9 i/o 1 i/o 8 i/o 0 oe gnd ce a0 a17 a7 a6 a5 a4 a3 a2 a1 n tf bga top view bottom view 8 7 6 5 4 3 2 1 a b c d e f g h j k l m ab cd e f g h j k l m top view a b c d e f g h j k l m 1 nc nc nc nc 2 nc nc a13 a12 a14 a15 a16 byte i/o 15 (a - 1) gnd nc nc 3 a9 a8 a10 a11 i/o 7 i/o 14 i/o 13 i/o 6 4 we reset nc a19 i/o 5 i/o 12 v cc i/o 4 5 ry/ by wp (acc) a18 a20 i/o 2 i/o 10 i/o 11 i/o 3 6 a7 a17 a6 a5 i/o 0 i/o 8 i/o 9 i/o 1 7 nc a3 a4 a2 a1 a0 ce oe gnd nc nc 8 nc nc nc nc
a29dl323 series preliminary (may, 2002, version 0.0) 3 amic technology, inc. block diagram address buffers bank / sector decoder state control (command register) address latch address latch x-decoder y-decoder cell matrix (bank 1) y-gating x-decoder y-decoder cell matrix (bank 2) y-gating sa / wc data latch sa / wc input / output buffers i/o 0 - i/o 15 (a-1) wp(acc) a0-a20 vcc gnd ry/by bank 1 address reset we byte ce oe bank 2 address program / erase voltage generator pin descriptions pin no. description a0 ? a20 address inputs i/o 0 - i/o 14 data inputs/outputs i/o 15 data input/output, word mode i/o 15 (a - 1) a - 1 lsb address input, byte mode ce chip enable we write enable oe output enable reset hardware reset input byte mode select ry/ by ready/ busy - output wp (acc) write protect (accelerated) input gnd ground vcc power supply nc note no connection note: some signals can be applied because this pin is not connected to the inside of the chip.
a29dl323 series preliminary (may, 2002, version 0.0) 4 amic technology, inc. input / output pin function pin name input / output function a0 to a20 input address input pins. a0 to a20 are used differently in the byte mode and the word mode. byte mode a0 to a20 are used as the upper 21 bits of total 22 bits of address input pin. (the least significant bit (a - 1) is combined to i/o 15 .) word mode a0 to a 20 are used as 21 bits address input pin. i/o 0 to i/o 14 input / output data input / output pins. i/o 0 to i/o 14 are used differently in the byte mode and the word mode. byte mode i/o 0 to i/o 7 are used as the 8 bits data input / output pins. i/o 8 to i/o 14 a re hi - z. word mode i/o 0 to i/o 14 are used as the lower 15 bits of total 16 bits of data input / output pins. (the most significant bit (i/o15) is combined to a - 1.) i/o 15 , a - 1 input / output i/o 15 , a1 are used differently in the byte mode and the word mode . byte mode the least significant address input pin (a - 1) word mode the most significant data input / output pin (i/o 15 ) ce input this pin inputs the signal that activates the chip. when high level, the chip enters the standby mode. oe input this pin inputs the read operation control signal. when high level, output is hi - z. we input this pin inputs the write operation control signal. when low level, command input is accepted. byte input the pin for switching byte mode and word mode. high level : word mode (2m words x 16 bits) low level : byte mode (4m words x 8 bits) reset input this pin inputs hardware reset. when low level, hardware reset is performed. if 11.5 to 12.5 v is applied to reset , the chip enters the temporary sector group unprotect mode. ry / by output this pin indicates whether automatic program / erase is currently being executed. it uses open drain con nection. low level indicates the busy state during which the device is performing automatic program erase. high level indicates the device is in the ready state and will accept the next operation. in this case, the device is either in the erase suspend mod e or the standby mode. wp (acc) input this pin selects the boot block sector protect mode or accelerated mode. low level: the boot block (2 sectors) is protected. high level: the boot block is unprotected. vacc level: accelerated mod e is selected. vcc - supply voltage gnd - ground nc - no connection
a29dl323 series preliminary (may, 2002, version 0.0) 5 amic technology, inc. absolute maximum ratings* storage temperature (t stg ) . . . . . . . . . . - 55 c to + 125 c operating ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40 c to + 85 c input / output voltage with respect to gnd wp (acc), reset . . . . . . . . . . . . - 0.5v note1 to 13.0v all pins except wp (acc), reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5v note1 to vcc + 0.4 (4.0v max.) note2 supply voltage with respect to gnd (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5v to 4.0v note s: 1. - 2.0v (min.) (pulse width 20ns) 2. vcc + 0.5v (max.) (pulse width 20ns) *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this devic e at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. recommended opera ting conditions operating ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40 c to +85 c supply voltage (vcc) . . . . . . . . . . . . . . . . . +2.7v to +3.6v bus operat ions the following table shows the operation modes of the dual operation flash memory. before turning on power, input gnd 0.2 v to the reset until vcc 3 vcc (min.). table 1. a29dl323 bus operations operation ce oe we i/o 15 , a - 1 a6 a1 a0 i/o 0 to i/o 7 i/o 8 to i/o 15 reset wp (acc) byte mode l l h a - 1 address input data output hi - z h x read (note) word mode l l h x address input dat a output h x write byte mode l h l a - 1 address input data input hi - z h note3 word mode l h l x address input data input h note3 standby h x x x x x x hi - z hi - z h x hardware reset / standby x x x x x x x hi - z hi - z l x output disable l h h x x x x hi - z hi - z h x temporary sector group unprotect x x x x x x x hi - z or data input / output v id note3 byte mode l l h a - 1 address input data output hi - z h x automatic sleep mode word mode l l h x address input data output h x boot block sector protect x x x x x x x hi - z or data input / output x l byte mode l h l a - 1 address input data input hi - z h vacc accelerated mode word mode l h l x address input data input h vacc note: when oe = v il , v il can be applied to we . when oe = v ih , a write operation is started. remarks: 1. h : v ih , l : v il , : v ih or v il , v id : 11.5 v to 12.5 v, vacc : 8.5 v to 9.5 v 2. if an address is held longer than the minimum read cycle time (t rc ), the automatic sleep mo de is set. 3. if wp (acc)=v il , sector 0,1,140, and 141 remain protected. if wp (acc)=v ih , protection on sectors 0,1,140, and 141 depends on whether they were last protected or unprotected using the method described i n ?sector/sector block protection and unprotection?. if wp (acc)=v hh , all sectors will be unprotected.
a29dl323 series preliminary (may, 2002, version 0.0) 6 amic technology, inc. read operation the read operation is controlled by the oe and /oe. the /ce is used to select a device, and t he oe controls data output. the following three access times are used depending on the condition. - address access time (t acc ): time until valid data is output after an address has been determined (however, after ce ) . - ce access time (t ce) : time until valid data is output after ce has been determined (however, after address). - oe access time (t oe ): time until valid data is output after oe has been determined (however, oe must be input after t acc - t oe , t ce - t oe after address and ce have been determined). on power - up, the device is automatically set in the read mode. to read the device without changin g address immediately after power application, either execute hardware reset or briefly lower ce to v il from v ih . for the timing waveform, refer to timing waveform for read cycle (1). write operation the operation of the device is con trolled by writing commands to the registers. the command register is a function that latches the address and data necessary for executing an instruction and does not occupy the memory area. if an illegal address or data is written or if an address or data is written in the wrong sequence, the device is reset to the read mode. standby mode the standby mode is set when v ih is input to the ce . the current consumption in the standby mode can be lowered to 5 m a or less in two ways. one is t o use ce and reset . input vcc 0.3 v to ce and reset . however, while automatic programming or erasing is being executed, the operating supply current (i cc2 ) does not decrease t o 5 m a or lower even if ce = v ih . if a read operation is executed in the standby mode, data is output at ce access time. the other is to input gnd 0.3 v to the reset . at this time, the level of ce is v ih or v il . in this case, t rh is required for the device to return to the read mode from the standby mode. for the timing waveform, refer to timing waveform for read cycle (2). hardware reset pin the device is reset to the read mode if v il is input to the reset for the duration of t rp and v ih for the duration of t rh . while v il is being input to the reset , all commands are ignored, and the output pins go into a hi - z state. if the voltage on reset is kept to gnd 0.2 v at this time, the current consumption can be lowered to 5 m a or less. if v ih is input to the reset , t ready is required until data is output. for the timing waveform, refer to timing waveform for read cycle (2). output disable mode output from the device is disabled (hi - z state) if v ih is input to the oe . sector group protection protect the sector group by using a command. oe or we con trol is no need. temporary sector group unprotect protection of a sector group can be temporarily canceled. when v id is input to reset , the temporary sector group unprotect mode is set. if a protected sector is selected in this mode, it can be programmed or erased. if the mode is canceled, the sector group is protected again. for the timing waveform, refer to timing waveform for temporary sector group unprotect. product id read the product id code by using a command. automatic sleep mo de the automatic sleep mode is used to reduce the power consumption substantially during a read operation. if an address is held longer than the minimum read cycle time (t rc ), the sleep mode (low power consumption mode) is automatically set. in this mode, the output data is latched and continuously output. in the automatic sleep mode, ce , we , and oe do not have to be controlled. at this time, the current consumption decreases to 5 m a or less. du ring dual operation, however, the current consumption is power supply current (i cc6 , i cc7 ). if the address is changed, the automatic sleep mode is canceled automatically, the device returns to the read mode, and the data of the newly input address is outpu t.
a29dl323 series preliminary (may, 2002, version 0.0) 7 amic technology, inc. boot block sector protect the boot block sector protect mode protects the two sectors of the boot block. this mode is set when v il is input to wp (acc). if v il is input to wp (acc) even in the temporary sector g roup unprotect mode, the boot block remains protected and protection of the other sectors is temporarily canceled. accelerated mode this mode is used to program the device at high speed, and the programming time can be shortened to about 60%. to program th e device in the accelerated mode, input vacc to wp (acc) and use an unlock bypass program command. therefore, ordinary commands can be used for programming or detection of completion of programming. if vacc is input to wp (acc), the device is automatically set in the unlock bypass mode. therefore, the unlock bypass set command and reset command are not necessary. the accelerated mode is automatically canceled if the input of vacc to wp (acc) is stopped. in the accelerated mode, protection of the sector group is temporarily canceled. exercise care in programming the device at this time. for the timing waveform, refer to timing waveform for accelerated mode. dual operation this device can execute a program or erase operation and a read operation simultaneously. by selecting bank 1 or 2 by changing the bank address, one bank can execute a read operation while the other bank is executing a program or erase operation. when changing the bank address, no wait cycle is necessary. note that two or more program or erase operation. when changing the bank address, no wait cycle is necessary. note that two or more operations cannot be executed at the same time in the same bank. the following table shows the combinations of bank operations. for the timing waveform, refer to timing waveform for dual operation. table 2. dual operation case operation of bank 1 operation of bank 2 1 read mode read mode 2 read mode product id 3 read mode program (note 1) 4 read mode erase (note 2) 5 product id read mode 6 program (note 1) read mode 7 erase (note 2) read mode notes 1. the program operation is suspended by the program suspend command, and addresses not being programmed to at this time can only be read. 2. the erase operation is suspended by the erase suspend command. the sector not erased at this time can be read or programmed.
a29dl323 series preliminary (may, 2002, version 0.0) 8 amic technology, inc. table 3. a29dl323 top boot block sector address table sector address table address ran ge (in hexadecimal) bank address table bank sector a20 a19 a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) byte mode (x 8) word mode (x16) sa70 1 1 1 1 1 1 1 1 1 8/4 3fffffh - 3fe000h 1fffffh - 1ff000h sa69 1 1 1 1 1 1 1 1 0 8/4 3fdfffh - 3fc000h 1fefffh - 1fe00 0h sa68 1 1 1 1 1 1 1 0 1 8/4 3fbfffh - 3fa000h 1fdfffh - 1fd000h sa67 1 1 1 1 1 1 1 0 0 8/4 3f9fffh - 3f8000h 1fcfffh - 1fc000h sa66 1 1 1 1 1 1 0 1 1 8/4 3f7fffh - 3f6000h 1fbfffh - 1fb000h sa65 1 1 1 1 1 1 0 1 0 8/4 3f5fffh - 3f4000h 1fafffh - 1fa000h sa64 1 1 1 1 1 1 0 0 1 8/4 3f3fffh - 3f2000h 1f9fffh - 1f9000h sa63 1 1 1 1 1 1 0 0 0 8/4 3f1fffh - 3f0000h 1f8fffh - 1f8000h sa62 1 1 1 1 1 0 x x x 64/32 3effffh - 3e0000h 1f7fffh - 1f0000h sa61 1 1 1 1 0 1 x x x 64/32 3dffffh - 3d0000h 1effffh - 1e8000h sa60 1 1 1 1 0 0 x x x 64/32 3cffffh - 3c0000h 1e7fffh - 1e0000h sa59 1 1 1 0 1 1 x x x 64/32 3bffffh - 3b0000h 1dffffh - 1d8000h sa58 1 1 1 0 1 0 x x x 64/32 3affffh - 3a0000h 1d7fffh - 1d0000h sa57 1 1 1 0 0 1 x x x 64/32 39ffffh - 390000h 1cffffh - 1c8000h sa56 1 1 1 0 0 0 x x x 64/32 38ffffh - 380000h 1c7fffh - 1c0000h sa55 1 1 0 1 1 1 x x x 64/32 37ffffh - 370000h 1bffffh - 1b8000h sa54 1 1 0 1 1 0 x x x 64/32 36ffffh - 360000h 1b7fffh - 1b0000h sa53 1 1 0 1 0 1 x x x 64/32 35ffffh - 350000h 1affffh - 1a8000h sa52 1 1 0 1 0 0 x x x 64/32 34ffffh - 340000h 1a7fffh - 1a0000h sa51 1 1 0 0 1 1 x x x 64/32 33ffffh - 330000h 19ffffh - 198000h sa50 1 1 0 0 1 0 x x x 64/32 32ffffh - 320000h 197fffh - 190000h sa49 1 1 0 0 0 1 x x x 64/32 31ffffh - 310000h 18ffffh - 188000h bank 1 sa48 1 1 0 0 0 0 x x x 64/3 2 30ffffh - 300000h 187fffh - 180000h sa47 1 0 1 1 1 1 x x x 64/32 2fffffh - 2f0000h 17ffffh - 178000h sa46 1 0 1 1 1 0 x x x 64/32 2effffh - 2e0000h 177fffh - 170000h sa45 1 0 1 1 0 1 x x x 64/32 2dffffh - 2d0000h 16ffffh - 168000h sa44 1 0 1 1 0 0 x x x 64 /32 2cffffh - 2c0000h 167fffh - 160000h sa43 1 0 1 0 1 1 x x x 64/32 2bffffh - 2b0000h 15ffffh - 158000h sa42 1 0 1 0 1 0 x x x 64/32 2affffh - 2a0000h 157fffh - 150000h sa41 1 0 1 0 0 1 x x x 64/32 29ffffh - 290000h 14ffffh - 148000h sa40 1 0 1 0 0 0 x x x 64/32 28ffffh - 280000h 147fffh - 140000h sa39 1 0 0 1 1 1 x x x 64/32 27ffffh - 270000h 13ffffh - 138000h sa38 1 0 0 1 1 0 x x x 64/32 26ffffh - 260000h 137fffh - 130000h sa37 1 0 0 1 0 1 x x x 64/32 25ffffh - 250000h 12ffffh - 128000h sa36 1 0 0 1 0 0 x x x 64/32 24ff ffh - 240000h 127fffh - 120000h bank 2 sa35 1 0 0 0 1 1 x x x 64/32 23ffffh - 230000h 11ffffh - 118000h
a29dl323 series preliminary (may, 2002, version 0.0) 9 amic technology, inc. table 3. a29dl323 top boot block sector address table (continued) sector address table address range (in hexadecimal) bank address table bank sector a20 a19 a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) byte mode (x 8) word mode (x16) sa34 1 0 0 0 1 0 x x x 64/32 22ffffh - 220000h 117fffh - 110000h sa33 1 0 0 0 1 1 x x x 64/32 21ffffh - 210000h 10ffffh - 108000h sa32 1 0 0 0 0 0 x x x 64/32 20ffffh - 200000h 107fffh - 100000h sa31 0 1 1 1 1 1 x x x 64/32 1fffffh - 1f0000h 0fffffh - 0f8000h sa30 0 1 1 1 1 0 x x x 64/32 1effffh - 1e0000h 0f7fffh - 0f0000h sa29 0 1 1 1 0 1 x x x 64/32 1dffffh - 1d0000h 0effffh - 0e8000h sa28 0 1 1 1 0 0 x x x 64/32 1cffffh - 1c0000h 0e7fffh - 0e0000h sa27 0 1 1 0 1 1 x x x 64/32 1bffffh - 1b0000h 0dffffh - 0d8000h sa26 0 1 1 0 1 0 x x x 64/32 1affffh - 1a0000h 0d7fffh - 0d0000h sa25 0 1 1 0 0 1 x x x 64/32 19ffffh - 190000h 0cffffh - 0c8000h sa24 0 1 1 0 0 0 x x x 64/32 18ffffh - 180000h 0c7fffh - 0c0000h sa23 0 1 0 1 1 1 x x x 64/32 17ffffh - 170000h 0bffffh - 0b8000h sa22 0 1 0 1 1 0 x x x 64/32 16ffffh - 160000h 0b7fffh - 0b0000h sa21 0 1 0 1 0 1 x x x 64/32 15ffffh - 150000h 0affffh - 0a8000h sa20 0 1 0 1 0 0 x x x 64 /32 14ffffh - 140000h 0a7fffh - 0a0000h sa19 0 1 0 0 1 1 x x x 64/32 13ffffh - 130000h 09ffffh - 098000h sa18 0 1 0 0 1 0 x x x 64/32 12ffffh - 120000h 097fffh - 090000h sa17 0 1 0 0 0 1 x x x 64/32 11ffffh - 110000h 08ffffh - 088000h sa16 0 0 1 0 0 0 x x x 64/32 10ffffh - 100000h 087fffh - 080000h sa15 0 0 1 1 1 1 x x x 64/32 0fffffh - 0f0000h 07ffffh - 078000h sa14 0 0 1 1 1 0 x x x 64/32 0effffh - 0e0000h 077fffh - 070000h sa13 0 0 1 1 0 1 x x x 64/32 0dffffh - 0d0000h 06ffffh - 068000h sa12 0 0 1 1 0 0 x x x 64/32 0cff ffh - 0c0000h 067fffh - 060000h sa11 0 0 1 0 1 1 x x x 64/32 0bffffh - 0b0000h 05ffffh - 058000h sa10 0 0 1 0 1 0 x x x 64/32 0affffh - 0a0000h 057fffh - 050000h sa9 0 0 1 0 0 1 x x x 64/32 09ffffh - 090000h 04ffffh - 048000h sa8 0 0 1 0 0 0 x x x 64/32 08ffffh - 08 0000h 047fffh - 040000h sa7 0 0 0 1 1 1 x x x 64/32 07ffffh - 070000h 03ffffh - 038000h sa6 0 0 0 1 1 0 x x x 64/32 06ffffh - 060000h 037fffh - 030000h sa5 0 0 0 1 0 1 x x x 64/32 05ffffh - 050000h 02ffffh - 028000h sa4 0 0 0 1 0 0 x x x 64/32 04ffffh - 040000h 02 7fffh - 020000h sa3 0 0 0 0 1 1 x x x 64/32 03ffffh - 030000h 01ffffh - 018000h sa2 0 0 0 0 1 0 x x x 64/32 02ffffh - 020000h 017fffh - 010000h sa1 0 0 0 0 0 1 x x x 64/32 01ffffh - 010000h 00ffffh - 008000h bank 2 sa0 0 0 0 0 0 0 x x x 64/32 00ffffh - 000000h 007fffh - 00 0000h
a29dl323 series preliminary (may, 2002, version 0.0) 10 amic technology, inc. table 4. a29dl323 bottom boot block sector address table sector address table address range (in hexadecimal) bank address table bank sector a20 a19 a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) byte mode (x 8) word mode (x16) sa70 1 1 1 1 1 1 x x x 64/32 3fffffh - 3f0000h 1fffffh - 1f8000h sa69 1 1 1 1 1 0 x x x 64/32 3effffh - 3e0000h 1f7fffh - 1f0000h sa68 1 1 1 1 0 1 x x x 64/32 3dffffh - 3d0000h 1effffh - 1e8000h sa67 1 1 1 1 0 0 x x x 64/32 3cffffh - 3c0000 h 1e7fffh - 1e0000h sa66 1 1 1 0 1 1 x x x 64/32 3bffffh - 3b0000h 1dffffh - 1d8000h sa65 1 1 1 0 1 0 x x x 64/32 3affffh - 3a0000h 1d7fffh - 1d0000h sa64 1 1 1 0 0 1 x x x 64/32 39ffffh - 390000h 1cffffh - 1c8000h sa63 1 1 1 0 0 0 x x x 64/32 38ffffh - 380000h 1c 7fffh - 1c0000h sa62 1 1 0 1 1 1 x x x 64/32 37ffffh - 370000h 1bffffh - 1b8000h sa61 1 1 0 1 1 0 x x x 64/32 36ffffh - 360000h 1b7fffh - 1b0000h sa60 1 1 0 1 0 1 x x x 64/32 35ffffh - 350000h 1affffh - 1a8000h sa59 1 1 0 1 0 0 x x x 64/32 34ffffh - 340000h 1a7fff h - 1a0000h sa58 1 1 0 0 1 1 x x x 64/32 33ffffh - 330000h 19ffffh - 198000h sa57 1 1 0 0 1 0 x x x 64/32 32ffffh - 320000h 197fffh - 190000h sa56 1 1 0 0 0 1 x x x 64/32 31ffffh - 310000h 18ffffh - 188000h sa55 1 1 0 0 0 0 x x x 64/32 30ffffh - 300000h 187fffh - 18 0000h sa54 1 0 1 1 1 1 x x x 64/32 2fffffh - 2f0000h 17ffffh - 178000h sa53 1 0 1 1 1 0 x x x 64/32 2effffh - 2e0000h 177fffh - 170000h sa52 1 0 1 1 0 1 x x x 64/32 2dffffh - 2d0000h 16ffffh - 168000h sa51 1 0 1 1 0 0 x x x 64/32 2cffffh - 2c0000h 167fffh - 160000 h sa50 1 0 1 0 1 1 x x x 64/32 2bffffh - 2b0000h 15ffffh - 158000h sa49 1 0 1 0 1 0 x x x 64/32 2affffh - 2a0000h 157fffh - 150000h sa48 1 0 1 0 0 1 x x x 64/32 29ffffh - 290000h 14ffffh - 148000h sa47 1 0 1 0 0 0 x x x 64/32 28ffffh - 280000h 147fffh - 140000h sa46 1 0 0 1 1 1 x x x 64/32 27ffffh - 270000h 13ffffh - 138000h sa45 1 0 0 1 1 0 x x x 64/32 26ffffh - 260000h 137fffh - 130000h sa44 1 0 0 1 0 1 x x x 64/32 25ffffh - 250000h 12ffffh - 128000h sa43 1 0 0 1 0 0 x x x 64/32 24ffffh - 240000h 127fffh - 120000h sa42 1 0 0 0 1 1 x x x 64/32 23ffffh - 230000h 11ffffh - 118000h sa41 1 0 0 0 1 0 x x x 64/32 22ffffh - 220000h 117fffh - 110000h sa40 1 0 0 0 0 1 x x x 64/32 21ffffh - 210000h 10ffffh - 108000h sa39 1 0 0 0 0 0 x x x 64/32 20ffffh - 200000h 107fffh - 100000h sa38 0 1 1 1 1 1 x x x 64/32 1fffffh - 1f0000h 0fffffh - 0f8000h sa37 0 1 1 1 1 0 x x x 64/32 1effffh - 1e0000h 0f7fffh - 0f0000h sa36 0 1 1 1 0 1 x x x 64/32 1dffffh - 1d0000h 0effffh - 0e8000h bank 2 sa35 0 1 1 1 0 0 x x x 64/32 1cffffh - 1c0000h 0e7fffh - 0e0000h
a29dl323 series preliminary (may, 2002, version 0.0) 11 amic technology, inc. table 4. a2 9dl323 bottom boot block sector address table (continued) sector address table address range (in hexadecimal) bank address table bank sector a20 a19 a18 a17 a16 a15 a14 a1 3 a12 sector size (kbytes/ kwords) byte mode (x 8) word mode (x16) sa34 0 1 1 0 1 1 x x x 64/32 1bffffh - 1b0000h 0dffffh - 0d8000h sa33 0 1 1 0 1 0 x x x 64/32 1affffh - 1a0000h 0d7fffh - 0d0000h sa32 0 1 1 0 0 1 x x x 64/32 19ffffh - 190000h 0cffffh - 0c8000h sa31 0 1 1 0 0 0 x x x 64/32 18ffffh - 180000h 0c7 fffh - 0c0000h sa30 0 1 0 1 1 1 x x x 64/32 17ffffh - 170000h 0bffffh - 0b8000h sa29 0 1 0 1 1 0 x x x 64/32 16ffffh - 160000h 0b7fffh - 0b0000h sa28 0 1 0 1 0 1 x x x 64/32 15ffffh - 150000h 0affffh - 0a8000h sa27 0 1 0 1 0 0 x x x 64/32 14ffffh - 140000h 0affffh - 0a0000h sa26 0 1 0 0 1 1 x x x 64/32 13ffffh - 130000h 09ffffh - 098000h sa25 0 1 0 0 1 0 x x x 64/32 12ffffh - 120000h 097fffh - 090000h sa24 0 1 0 0 0 1 x x x 64/32 11ffffh - 110000h 08ffffh - 088000h bank 2 sa23 0 1 0 0 0 0 x x x 64/32 10ffffh - 100000h 087fffh - 0 80000h sa22 0 0 1 1 1 1 x x x 64/32 0fffffh - 0f0000h 07ffffh - 078000h sa21 0 0 1 1 1 0 x x x 64/32 0effffh - 0e0000h 077fffh - 070000h sa20 0 0 1 1 0 1 x x x 64/32 0dffffh - 0d0000h 06ffffh - 068000h sa19 0 0 1 1 0 0 x x x 64/32 0cffffh - 0c0000h 067fffh - 06000 0h sa18 0 0 1 0 1 1 x x x 64/32 0bffffh - 0b0000h 05ffffh - 058000h sa17 0 0 1 0 1 0 x x x 64/32 0affffh - 0a0000h 057fffh - 050000h sa16 0 0 1 0 0 1 x x x 64/32 09ffffh - 090000h 04ffffh - 048000h sa15 0 0 1 0 0 0 x x x 64/32 08ffffh - 080000h 047fffh - 040000h sa14 0 0 0 1 1 1 x x x 64/32 07ffffh - 070000h 03ffffh - 038000h sa13 0 0 0 1 1 0 x x x 64/32 06ffffh - 060000h 037fffh - 030000h sa12 0 0 0 1 0 1 x x x 64/32 05ffffh - 050000h 02ffffh - 028000h sa11 0 0 0 1 0 0 x x x 64/32 04ffffh - 040000h 027fffh - 020000h sa1 0 0 0 0 0 1 1 x x x 64/32 03ffffh - 030000h 01ffffh - 018000h sa9 0 0 0 0 1 0 x x x 64/32 02ffffh - 020000h 017fffh - 010000h sa8 0 0 0 0 0 1 x x x 64/32 01ffffh - 010000h 00ffffh - 008000h sa7 0 0 0 0 0 0 1 1 1 64/32 00ffffh - 00e000h 007fffh - 007000h sa6 0 0 0 0 1 1 1 1 0 64/32 00dfffh - 00c000h 006fffh - 006000h sa5 0 0 0 0 0 0 1 0 1 64/32 00bfffh - 00a000h 005fffh - 005000h sa4 0 0 0 0 0 0 1 0 0 64/32 009fffh - 008000h 004fffh - 004000h sa3 0 0 0 0 0 0 0 1 1 64/32 007fffh - 006000h 003fffh - 003000h sa2 0 0 0 0 0 0 0 1 0 64/32 005fffh - 004000h 002fffh - 002000h sa1 0 0 0 0 0 0 0 0 1 64/32 003fffh - 002000h 001fff - 001000h bank 1 sa0 0 0 0 0 0 0 0 0 0 64/32 001fffh - 000000h 000fffh - 000000h
a29dl323 series preliminary (may, 2002, version 0.0) 12 amic technology, inc. table 5. a29dl323 top boot sector group address table sector group a20 a19 a18 a17 a16 a15 a14 a13 a12 size sector sga0 0 0 0 0 0 0 x x x 64 kb (1 sector) fsa0 0 1 1 0 sga1 0 0 0 0 1 1 x x x 192 kb (3 sectors) fsa1 ? fsa3 sga2 0 0 0 1 x x x x x 256 kb (4 sectors) fsa4 ? fsa7 sga3 0 0 0 1 x x x x x 256 kb (4 sectors) fsa 8 ? fsa11 sga4 0 0 1 1 x x x x x 256 kb (4 sectors) fsa12 ? fsa15 sga5 0 1 0 0 x x x x x 256 kb (4 sectors) fsa16 ? fsa19 sga6 0 1 0 1 x x x x x 256 kb (4 sectors) fsa20 ? fsa23 sga7 0 1 1 0 x x x x x 256 kb (4 sectors) fsa24 ? fsa27 sga8 0 1 1 1 x x x x x 256 kb (4 sectors) fsa28 ? fsa31 sga9 0 1 1 1 x x x x x 256 kb (4 sectors) fsa32 ? fsa35 sga10 1 0 0 1 x x x x x 256 kb (4 sectors) fsa36 ? fsa39 sga11 1 0 1 0 x x x x x 256 kb (4 sectors) fsa40 ? fsa43 sga12 1 0 1 1 x x x x x 256 kb (4 sectors) fsa44 ? fsa47 sga13 1 1 0 0 x x x x x 256 kb (4 sectors) fsa48 ? fsa51 sga14 1 1 0 1 x x x x x 256 kb (4 sectors) fsa52 ? fsa55 sga15 1 1 1 0 x x x x x 256 kb (4 sectors) fsa56 ? fsa59 0 0 0 1 sga16 1 1 1 1 1 0 x x x 192 kb (3 sectors) fsa60 ? fsa62 sga17 1 1 1 1 1 1 0 0 0 8 kb (1 sector) fsa63 sga18 1 1 1 1 1 1 0 0 1 8 kb (1 sector) fsa64 sga19 1 1 1 1 1 1 0 1 0 8 kb (1 sector) fsa65 sga20 1 1 1 1 1 1 0 1 1 8 kb (1 sector) fsa66 sga21 1 1 1 1 1 1 1 0 0 8 kb (1 sector) fsa67 sga22 1 1 1 1 1 1 1 0 1 8 kb (1 sector) fsa68 sga23 1 1 1 1 1 1 1 1 0 8 kb (1 sector) fsa69 sga24 1 1 1 1 1 1 1 1 1 8 kb (1 sector) fsa70 remark x: v ih or v il
a29dl323 series preliminary (may, 2002, version 0.0) 13 amic technology, inc. table 6. a29dl323 bottom boot sector group address table sector group a20 a19 a18 a17 a16 a15 a14 a13 a12 size sector sga0 0 0 0 0 0 0 0 0 0 8 kb (1 sector) fsa0 sga1 0 0 0 0 0 0 0 0 1 8 kb (1 sector) fsa1 sga2 0 0 0 0 0 0 0 1 0 8 kb (1 sector) fsa2 sga3 0 0 0 0 0 0 0 1 1 8 kb (1 sector) fsa3 sga4 0 0 0 0 0 0 1 0 0 8 kb (1 sector) fsa4 sga5 0 0 0 0 0 0 1 0 1 8 kb (1 sector) fsa5 sga6 0 0 0 0 0 0 1 1 0 8 kb (1 sector) fsa6 sga7 0 0 0 0 0 0 1 1 1 8 kb (1 sector) fsa7 sga8 0 0 0 0 0 1 x x x 192 kb (3 sectors) fsa8 ? fsa10 1 0 1 1 sga9 0 0 0 1 x x x x x 256 kb (4 sectors) fsa11 ? fsa14 sga10 0 0 1 0 x x x x x 256 kb (4 sectors) fsa15 ? fsa18 sga11 0 0 1 1 x x x x x 256 kb (4 sectors) fsa19 ? fsa22 sga12 0 1 0 0 x x x x x 256 kb (4 sectors) fsa23 ? fsa26 sga13 0 1 0 1 x x x x x 256 kb (4 sectors) fsa27 ? fsa30 sga14 0 1 1 0 x x x x x 256 kb (4 sectors) f sa31 ? fsa34 sga15 0 1 1 1 x x x x x 256 kb (4 sectors) fsa35 ? fsa38 sga16 1 0 0 0 x x x x x 256 kb (4 sectors) fsa39 ? fsa42 sga17 1 0 0 1 x x x x x 256 kb (4 sectors) fsa43 ? fsa46 sga18 1 0 1 0 x x x x x 256 kb (4 sectors) fsa47 ? fsa50 sga19 1 0 1 1 x x x x x 256 kb (4 sectors) fsa51 ? fsa54 sga20 1 1 0 0 x x x x x 256 kb (4 sectors) fsa55 ? fsa58 sga21 1 1 0 1 x x x x x 256 kb (4 sectors) fsa59 ? fsa62 sga22 1 1 1 0 x x x x x 256 kb (4 sectors) fsa63 ? fsa66 0 0 0 1 sga23 1 1 1 1 1 0 x x x 192 kb (3 sector) fsa67 ? fsa6 9 sga24 1 1 1 1 1 1 x x x 64 kb (1 sector) fsa70 remark x: v ih or v il
a29dl323 series preliminary (may, 2002, version 0.0) 14 amic technology, inc. table 7. a29dl323 product id code (manufacture code / device code) input output product id code a12 to a20 a6 a1 a0 a - 1 note 1 i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 hex manufacturer code x v il v il v il v il 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 10h top boot hi - z hi - z hi - z hi - z hi - z hi - z hi - z hi - z 0 1 0 1 0 0 0 0 50h byte mode bottom boot x v il v il v il v il hi - z hi - z hi - z hi - z hi - z hi - z hi - z hi - z 0 1 0 1 0 0 1 1 53h top boot 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 2250h device code wor d mode bottom boot x v il v il v ih x 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 1 2253h sector group protection sector group a ddress v il v ih v il v il 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 01h note2 notes: 1. a - 1 is valid only in the byte mode. i/o 8 to i/o 14 go into a high - impedance state in the byte mode, and i/o 15 is a - 1 of the lowest address. 2. if 01h is output, the sector group is protected. if 00h is output, the sector group is unprotected. remark x: v ih or v il
a29l323 series preliminary (may, 2002, version 0.0) 15 amic technology, inc. sector group protection this command performs sector group protection. by applying v id to reset and writing 60h to any address, the device enters t he sector group protection mode. sector group protection is started by inputting the sector group address of the sector group to be protected to a12 to a20, inputting (a6, a1, a0) = (v il , v ih , v il ), and writing 60h. after a timeout of 250 m s, sector group p rotection is completed. next, with the sector group address input to a12 to a20, the device enters the sector group protection verify mode by inputting (a6, a1, a0) = (v il , v ih , v il ), and writing 40h. when read is performed in this state, the sector group protection verify result is output to i/o0. if "1" is output to i/o0, the verified sector group is protected. if "1" was not output to i/o0, sector group protection failed, so perform sector group protection again. for the timing waveform and flow chart , refer to timing waveform for sector group protection and figure 1. sector group unprotect this command performs sector group unprotect. sector group unprotect is performed for all sector group. unprotect cannot be performed for specific sector group. moreover, all sector groups must be protected priors to unprotect. the device enters the sector group unprotect mode by applying vid to reset and writing 60h to any address. if unprotected sector group exist, first perform sector group pr otection for these sector groups. to protect a sector group, input the sector group address of the sector group to be protected to the sector group address input pin, input (a6, a1, a0) = (v il , v ih , v il ), and write 60h (refer to sector group protection). s ector group unprotect is started by inputting (a6, a1, a0) = (v ih, v ih , v il ), and writing 60h to any address. following a timeout of 15 ms, sector group unprotect is completed. unprotect verification must be performed for each sector group. the device ente rs the sector group unprotect verification mode by inputting the sector group address to input pin of sector group address and writing 40h, with input (a6, a1, a0) = (v ih , v ih , v il ). if reading is performed in this state, the sector group unprotect verific ation result is output to i/o 0 . if the verified sector group is unprotected, "0" is output to i/o 0 . if "0" is not output to i/o 0 , this means that unprotect failed, so perform sector group unprotect again. for the flow chart, refer to figure 2. sector gro up unprotect flow chart. query the dual operation flash memory conforms to cfi (common flash memory interface). cfi enables information about a device such as the device specifications, memory density, and supply voltage to be read. therefore, the softwa re of the host system can support the software algorithm of a specific vendor used by a device by using the cfi. for details, refer to the cfi specifications. by writing the query command (98h) and giving an address, the device information corresponding t o that address can be read. if the device information is read in the word mode (16 bits), the upper bytes of data (i/o 15 to i/o 8 ) are "0". to end the query mode, writes the read / reset command. extra one time protect sector entry the dual operation flas h memory has a sector area that has one time protect function. this area does not allow code that has been written to the area to be changed. this area can be programmed or erased until it is protected. once it has been protected, however, protection can n ever be canceled. therefore, care must be exercised when using this area. the extra one time protect sector area has a density of 64 kbytes and exits at the same addresses as the 8 kbytes sector. these addresses are 3f0000h to 3fffffh for top boot in the b yte mode (1f8000h to 1fffffh in the word mode), and 000000h to 00ffffh for bottom boot in the byte mode (000000h to 007fffh in the word mode). because boot block areas (8 kbytes x 8 sectors) usually appear in the areas of these addresses, the extra one tim e protect sector entry command sequence must be written to enter them as the extra one time protect sector area. the status in which the extra one time protect sector area appears is the extra one time protect sector mode. in the extra one time protect sec tor mode, the other sectors, except the boot block area, can be read. in addition, the extra one time protect sector area can be read, programmed, or erased in this mode. to exit from the extra one time protect sector mode, the extra one time protect sect or reset command sequence must be written. extra one time protect sector program to program data to the extra one time protect sector area, write the extra one time protect sector program command sequence in the extra one time protect sector mode. this co mmand is no different from the conventional program command except that it must be written in the extra one time protect sector mode. therefore, completion of execution of this command is detected in the same manner as the conventional detection method of using i/o 7 data polling, i/o 6 toggle bit, and ry/ by . care must be exercised in selecting a program destination address. if a program destination address other than the one in the extra one time protect sector area is selected, the data of that address is changed.
a29dl323 series preliminary (may, 2002, version 0.0) 16 amic technology, inc. extra one time protect sector erase to erase the extra one time protect sector area, write the extra one time protect sector erase command sequence in the extra one time protect sector mode. this command is the same as the con ventional sector erase command except that it must be written in the extra one time protect sector mode. therefore, completion of execution of this command is detected in the same manner as the conventional detection method of using i/o 7 data polling, i/o 6 toggle bit, and ry/ by . care must be exercised in selecting a sector address to erase. if a sector address other than the one in the extra one time protect sector area is selected, the data of that sector is changed. extra one time pro tect sector protection the following write operations are used to protect the extra one time protect area during the extra one time protect sector mode. write the sector group protection setup command (60h) in the extra one time protect sector mode. . set (a6, a1, a0) = (v il , v ih , v il ), and set the sector address that selects the extra one time protect sector. . write the sector group protection command (60h). because the sequence is the same as the conventional command sequence to protect a sector group except that the extra one time protect sector mode must be set and that vid is not input to the reset , the same command sequence can be used. for details of how to protect a sector group, refer to sector group protection. if an address o ther than the one of the extra one time protect sector area is specified as a sector address, the other sectors are affected. once the sector has been protected, protection can never be canceled. exercise utmost care when protecting a sector. hardware da ta protection this device requires two unlock cycles for program / erase command sequence to prevent illegal program / erase. moreover, a hardware data protect function is provided as follows. low vcc write inhibit to prevent an illegal write cycle during vcc transition, the command register and program / erase circuit is disabled and all write cycles are ignored while vcc is v lko or lower. write commands are ignored until vcc becomes equal to or greater than v lko . logical inhibit the write cycle is inhibi ted under any of the following conditions : oe = v il , ce = v ih , or we = v ih . to start a write cycle, ce = v il and we = v il must be set while /oe = v ih . power - up write inhibit even if we = ce = v il and oe = v ih are satisfied at power - up, no commands are accepted at the rising edge of we . the device is automatically reset to the read mode at power on. write pulse "glitch" protection because oe , ce , and /we reject a noise pulse of 5 ns (typical) or less as an invalid pulse, a write operation is not started. sector group protection th e dual operation flash memory can be protected by the user in sector group units. for details, refer to sector group protection.
a29l323 series preliminary (may, 2002, version 0.0) 17 amic technology, inc. start reset=v id wait 4 us protect sector group? pulse count=1 sector group protection (a6, a1, a0)=(v il , v ih , v il ), address=sga, data=60h timeout 250us verify sector group protection (a6, a1, a0)=(v il , v ih , v il ), address=sga, data=40h read from sector group address (a6, a1, a0)=(v il , v ih , v il ), address=sga data=01h? protect other sector group? remove v id from reset, write reset command sector group protect complete temporary sector group unprotect mode no yes yes no yes sector group protection (unprotect) mode address=don't care data=60h next sector group address increment pulse count data=01h? no no remove vid from reset, write reset command yes fail figure 1. sector group protection flow chart
a29l323 series preliminary (may, 2002, version 0.0) 18 amic technology, inc. start reset=v id wait 4 us all sector group protected? verify sector group protection (a6, a1, a0)=(v il , v ih , v il ) a12 to a20=sga, data=40h read from sector group address (a6, a1, a0)=(v il , v ih , v il ), a12 to a20=sga n=0, pluse count=1 verify sector group protection (a6, a1, a0)=(v ih , v ih , v il ), address=sga, data=40h read from sector group address (a6, a1, a0)=(v ih , v ih , v il ), a12 to a20=sga data=00h? last sector group (n=25)? remove v id from reset, write reset command sector group protect complete no yes yes yes no n=0 next sector group address (n=n+1) increment pulse pulse count=1000? no no remove vid from reset, write reset command yes fail figure 2. sector group unprotect flow chart sector group protection address=don't care, data=60h data=0h? last sector group (n=25)? yes yes sector group unprotect (a6, a1, a0)=(v ih , v ih , v il ), data=60h timeout 15ms next sector group address (n=n+1) sector group protection no yes
a29l323 series preliminary (may, 2002, version 0.0) 19 amic technology, inc. cfi code list address a6 to a0 data i/o 15 to i/o 0 description 10h 11h 12h 0051h 0052h 0059h "qry" (ascii code) 13h 14h 0002h 0000h main command set 2 : amd/fj standard type 15h 16h 0040h 0000h start address of primary table 17h 18h 0000h 0000h auxiliary command set 00h : not supported 19h 1ah 0000h 0000h start addre ss of auxiliary algorithm table 1bh 0027h minimum vcc voltage (program / erase) i/o 7 to i/o 4 : 1 v/bit i/o 3 to i/o 0 : 100 mv/bit 1ch 0036h maximum vcc voltage (program / erase) i/o 7 to i/o 4 : 1 v/bit i/o 3 to i/o 0 : 100 mv/bit 1dh 0000h minimum vpp volta ge 1eh 0000h maximum vpp voltage 1fh 0004h typical word program time (2 n s) 20h 0000h typical buffer program time (2 n s) 21h 000ah typical sector erase time (2 n ms) 22h 0000h typical chip erase time (2 n ms) 23h 0005h maximum word program time (typ ical time 2 n ) 24h 0000h maximum buffer program time (typical time 2 n ) 25h 0004h maximum sector erasing time (typical time 2 n ) 26h 0000h maximum chip erasing time (typical time 2 n ) 27h 0016h capacity (2 n bytes) 28h 29h 0002h 0000h i/o informati on 2 : 8/16 - bit organization 2ah 2bh 0000h 0000h maximum number of bytes when two banks are programmed (2 n ) 2ch 0002h type of erase block 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h information about erase block 1 bit0 to 15 : y = number of sectors bit16 to 31 : z = size (z 256 bytes) 31h 32h 33h 34h 003eh 0000h 0000h 0001h information about erase block 2 bit0 to 15 : y = number of sectors bit16 to 31 : z = size (z 256 bytes) 40h 41h 42h 0050h 0052h 0049h "pri" (ascii code)
a29dl323 series preliminary (may, 2002, version 0.0) 20 amic technology, inc. cfi code list (continued ) address a6 to a0 data i/o 15 to i/o 0 description 43h 0031h main version (ascii code) 44h 0032h minor version (ascii code) 45h 0000h address during command input 00h : necessary 01h : unnecessary 46h 0002h temporary erase suspend function 00h : not sup ported 01h : read only 02h : read / program 47h 0001h sector group protection 00h : not supported 01h : supported 48h 0001h temporary sector group protection 00h : not supported 01h : supported 49h 0004h sector group protection algorithm 4ah 00xxh numb er of sectors of bank 2 00h : not supported 30h : a29dl323 4bh 0000h burst mode 00h : not supported 4ch 0000h page mode 00h : not supported 4dh 0085h minimum v acc voltage i/o 7 to i/o 4 : 1 v/bit i/o 3 to i/o 0 : 100 mv/bit 4eh 0095h maximum v acc voltage i/o 7 to i/o 4 : 1 v/bit i/o 3 to i/o 0 : 100 mv/bit 4fh 00xxh boot organization 02h : bottom boot (a29dl323ux - xx) 03h : top boot (a29dl323tx - xx) 50h 0001h temporary program suspend function 00h : not supported 01h : supported
a29dl323 series preliminary (may, 2002, version 0.0) 21 amic technology, inc. command definitions writing commands all operations are executed by writing a command. to write a command, the write cycle of a standard microprocessor is used. the operation of the device is controlled by writing a command to a register. the command register is a function that lat ches the address and data necessary for executing an instruction and does not occupy the memory area. if an illegal address or data is written or if an address or data is written in the wrong sequence, the device is reset to the read mode. table 8. shows t he commands and command sequences. read / reset command this command resets the device to the read mode. the read mode is maintained until the contents of the command register are changed. once the device is in the read mode, no command is necessary for reading data. data read can be performed using the read cycle of a standard microprocessor. the read mode is maintained until the contents of the command register are changed. product id the manufacturer code and device code can be read without inputting a high voltage to the address pin. if a bank address is specified in the third bus cycle and a read operation is started from address xx00h in the fourth bus cycle, manufacturer code 10h is output. if address xx02h (byte mode) or xx01h (word mode) is read , the device code is output. if a read operation is executed from an address in the bank not specified in the third bus cycle, data of the memory cell is output. if a read operation is executed starting from address (ba) 02h (word mode) or (ba) 04h (byte m ode), information indicating which sector group is protected can be obtained. if the sector group address is scanned with (a6, a1, a0) = (v il , v ih , v il ), "1" is output to i/o 0 to indicate that the sector group is protected (for details refer to sector grou p protection). the product id can be read only from the specified bank. to read the manufacturer code, device code, and information on protection of sector group from a bank not specified, write the read / reset command, specify the bank address to be read , and then write the product id command again. to end the product id mode, writes the read / reset command. to write the product id command in the product id mode, execute the read / reset command once. program command sequence this command is used to prog ram data. program is performed in 1 byte or 1 word units. program can be performed regardless of the address sequence, even if the sector limit is exceeded. however, "0" cannot be changed back into "1" through the program operation. if overwriting "1" to " 0" is attempted, the program operation is interrupted and "1" is output to i/o 5 , or successful program is indicated in data polling, but actually the data is "0" as before. following write by command sequence, the pulse required for program is automaticall y generated inside the device and program verification is automatically performed, so that control from external is not required. during automatic program, any command other than the program suspend is ignored. however, automatic program is interrupted wh en hardware reset is performed. since the programmed data is not guaranteed in this case, reexecute the program command following completion of reset. upon completion of automatic program, the device returns to the read mode. the operation status of auto matic program can be determined by using the hardware sequence flags (i/o 7 , i/o 6 , ry/ by pins). see sections ?i/o 7 (data polling)?, ?i/o 6 (toggle bit)?, and ?ry/ by (ready / busy )?. for the timing waveform and flow chart, refer to timing waveform for write cycle ( we controlled), timing waveform for write cycle ( ce controlled) and figure 3. start write program command sequence data poll from system last address ? programming completed no yes yes increment address figure 3. program flow chart
a29dl323 series preliminary (may, 2002, version 0.0) 22 amic technology, inc. program suspend / resume commands this command is used to suspend automatic programming. addresses not being programmed to while programming is suspended can be read. sector erase (including the timeout period) and data program operations can be both suspended. chip erase operations cannot be suspended. 1 m s is required between when the command sequence is programmed and when the automatic program operation is suspended. the execution status of an automatic program operation can be determined using a hardware sequence flag (i/o 7 , i/o 6 pins.) ref er to i/o 7 (data polling) and i/o 6 (toggle bit). to resume an automatic program operation, write the resume command (30h) while the operation is suspended. caution about program suspend / resume commands if automatic program resume and suspend are repeate d at intervals of less than 5 m s, the program operation may not be correctly completed. chip erase command sequence this command is used to erase the entire chip. following command sequence write, erase is performed after "0" is written to all memory cells and verification is performed, using the automatic erase function. program before erase and control from external are not required. during automatic erase, all commands that have been written are ignored. however, automatic erase is interrupted by hard ware reset. since erase is not guaranteed in this case, execute the chip erase command again after reset is completed. upon completion of automatic erase, the device returns to read mode. the automatic erase operation status can be determined with the hard ware sequence flags (i/o 7 , i/o 6 , ry/ by pins). see sections ?i/o 7 (data polling)?, ?i/o 6 (toggle bit)?, and ?ry/ by (ready / busy )?. for the timing waveform and flow chart, refer to timing waveform for sector / chip erase and figure 4. sector erase command sequence this command is used to erase data in sector units. "0" is written to the entire sector whose data is to be erased by the automatic erase function after the command sequence has been wri tten, and erase is executed after verification has been performed. programming before erase and external control are not necessary. the timeout period of sector erase starts when erase command 30h and the address of the sector to be erased are written at the sixth bus cycle. when this timeout period (50 m s) has elapsed, the device automatically starts erasing. two or more sectors can be selected and erased at the same time by additionally writing erase command 30h and the address of the sector whose data is to be erased during the timeout period. in this case, the timeout period starts again after the last erase command has been written. if a protected sector and a sector that is not protected are included in the selected sectors, only the sector that is no t protected is erased and the protected sector is ignored. if a command other than the sector erase or erase suspend command is input during the timeout period, the device is reset to the read mode. if the timeout period has elapsed and erase has started, any command other than the erase suspend command is ignored. however, erase is stopped if hardware reset is executed. in this case, sector erase is not guaranteed. execute the sector erase command again after completion of reset. when automatic erasure has been completed, the device returns to the read mode. completion of automatic sector erase can be reported to the host system by using the data polling function of i/o 7 , toggle bit function of i/o 6 , and ry/ by pin. sector erase is star ted after the lapse of the timeout period that is started from the rising of the we or ce pulse, whichever earlier, of the last sector erase command and is completed when the data of i/o 7 is set to "1" (refer to ha rdware sequence flags). the device returns to the read mode. data polling and toggle bit function in any address of the sector that is to be erased. the time required to erase two or more sectors is "(sector programming time + sector erase time) x number o f sectors". if two or more sectors of different banks are erased, a read operation from a bank (i.e., dual operation) cannot be executed. for the timing waveform and flow chart, refer to timing waveform for sector / chip erase and figure 4. start write erase command sequence data poll from system data = ffh ? erasure completed yes no figure 4. sector / chip erase flow chart
a29dl323 series preliminary (may, 2002, version 0.0) 23 amic technology, inc. sector eras e suspend / resume commands this command suspends automatic erase. during erase suspend, sectors for which erase is not performed can be read and programmed. sector erase (including the timeout period) and data program operations can be both be suspended. chip erase operations cannot be suspended. suspend can be performed for all sectors for which erase is being performed. following command sequence write, 20 m s are required until automatic erase is suspended. while automatic erase is suspended, any sector for which erase is not being performed can be read and programmed. whether automatic erase is suspended can be determined with the hardware sequence flags (i/o 7 , i/o 6 , i/o 2 pins). see sections ?i/o7 (data polling)?, ?i/o6 (toggle bit)?, and ?i/o2 (toggle b it ii)". if resume automatic erase that has been suspended, write the resume command (30h) while sector erase is suspended. at this time, input a bank address of the sector for which erasure is suspended. caution sector erase suspend / resume commands if a utomatic erase resume and suspend are repeated at intervals of less than 100 m s, the erasure operation may not be correctly completed. unlock bypass command sequence this device provides an unlock bypass mode to shorten the program time. normally, 4 write c ycle included with 2 unlock cycles are required during program. in contrast, with the unlock bypass mode, it is possible to perform program without unlock cycles. in the unlock bypass mode, all commands except unlock bypass program and unlock bypass reset are ignored. to end the unlock bypass mode, the unlock bypass reset command must be written. note, however, that the unlock bypass reset command must be written to an address of the bank that is not being read in dual operation. if the unlock bypass reset command is written, the device returns to the normal read mode. in the unlock bypass mode, the operating current is necessary even if ce = v ih . for the flowchart, refer to figure 5. unlock bypass set this command sets the device to th e unlock bypass mode. unlock bypass program this command is used to perform program in the unlock bypass mode. unlock bypass reset this command is used to quit the unlock bypass mode. when this command is executed, the device returns to the read mode. start address=555h data=aah address=2aah data=55h last address ? end no yes figure 5. unlock bypass flow chart (word mode) address=don't care data=a0h address=program address data=program data data polling programming completed address=don't care data=00h note: this flow chart shows the word mode's case. in the byte mode, address to be input is different from the word mode. see table 8. command sequence address=555h data=20h address=ba data=90h unlock bypass set unlock bypass program unlock bypass reset next address
a29l323 series preliminary (may, 2002, version 0.0) 24 amic technology, inc. table 8. a29dl323 command sequence command sequence bus cycle 1 st bus cycle 2 nd bus cycle 3 rd bus cycle 4 th bus cycle 5 th bus cycle 6 th bus cycle address data address data address data address data address data address dat a read / reset note 1 1 xxxh f0h ra rd - - - - - - - - byte mode 3 aaah aah 555h 55h aaah f0h ra rd - - - - read / reset note 1 word mode 555h 2aah 555h byte mode 4 aaah aah 555h 55h aaah a0h pa pd - - - - program word mode 555h 2aah 55 5h program suspend note2 1 ba b0h - - - - - - - - - - program suspend note3 1 ba 30h - - - - - - - - - - byte mode 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h aaah 10h chip erase word mode 555h 2aah 555h 555h 2aah 555h b yte mode 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h fsa 30h sector erase word mode 555h 2aah 555h 555h 2aah sector erase suspend note4 1 ba b0h - - - - - - - - - - sector erase suspend resume note5 1 ba 30h - - - - - - - - - - byte mo de 3 aaah aah 555h 55h aaah 20h - - - - - - unlock bypass set word mode 555h 2aah 555h unlock bypass program note6 2 xxxh a0h pa pd - - - - - - - - unlock bypass reset note7 2 ba 90h xxxh 00h note11 - - - - - - - - byte mode 3 aaah aah 555h 55h (ba) aaah 90h ia id - - - - product id word mode 555h 2aah (ba) 555h sector group protection note7 4 xxxh 60h spa 60h spa 40h spa sd - - - - sector group unprotect note8 4 xxxh 60h sua 60h sua 40h sua sd - - - - byte mode 1 aah 98h - - - - - - - - - - query note9 word mode 55h byte mode 3 aaah aah 555h 55h aaah 88h - - - - - - extra one time protect sector entry word mode 555h 2aah 555h byte mode 4 aaah aah 555h 55h aaah a0h pa pd - - - - extra one time protect sector program note10 word mode 555h 2aah 555h byte mode 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h eotpsa 30h extra one time protect sector erase note10 word mode 555h 2aah 555h 555h 2aah byte mode 4 aa ah aah 555h 55h aaah 90h xxxh 00h - - - - extra one time protect sector reset note10 word mode 555h 2aah 555h extra one time protect sector protection note10 4 xxxh 60h eotpsa 60h eotpsa 40h eotpsa sd - - - - note: 1. both these read / reset commands reset the device to the read mode. 2. pr ogramming is suspended if b0h is input to the bank address being programmed to in a program operation. 3. programming is resumed if 30h is input to the bank address being suspended to in a program - suspend operation. 4. erasure is suspended if b0h is input to the bank address being erased in a sector erase operation. 5. erasure is resumed if 30h is input to the bank address being suspended in a sector - erase - suspend operation. 6. valid only in the unlock bypass mode. 7. valid only when reset = v id (except in the extra one time protect sector mode). 8. the command sequence that protects a sector group is excluded.
a29dl323 series preliminary (may, 2002, version 0.0) 25 amic technology, inc. 9. only a0 to a6 are valid as an address. 10. valid only in the extra one time protect sector mode. 11. this command can be used even if this data is f0h. rem arks: 1. specify address 555h or 2aah (a10 to a0) in the word mode, and aaah or 555h (a10 to a0, a - 1) in the byte mode. 2. ra : read address rd : read data ia : address input xx00h (to read the manufacturer code) xx02h (to read the device code in the byte mode) xx01h (to read the device code in the word mode) id : code output. refer to the product id code (manufacturer code / device code). pa : program address pd : program data fsa: erase sector address. the sector to be erased is selected by the comb ination of this address. refer to the sector organization / sector address table. ba : bank address. refer to the sector organization / sector address table. spa : sector group address to be protected. set sector group address (sga) and (a6, a1, a0) = ( v il , v ih , v il ). sua : unprotect sector group address. set sector group address (sga) and (a6, a1, a0) = (v ih , v ih , v il ). eotpsa : extra one time protect sector area addresses. these addresses are 3f0000h to 3fffffh (byte mode) / 1f8000h to 1fffffh (word mode) for top boot, and 000000h to 00ffffh (byte mode) / 000000h to 007fffh (word mode) for bottom boot. sd : data for verifying whether sector groups read from the address specified by spa, sua, and eotpsa are protected or unprotected. 3. the sector group address is don't care except when a program / erase address or read address are selected. 4. of address bit indicates v ih or v il .
a29dl323 series preliminary (may, 2002, version 0.0) 26 amic technology, inc. hardware sequence flags the status of automatic program / erase operations can be determined from the status of the i/o2, i /o3, i/o5, i/o6, i/o7, and ry / by pins. caution when reading flags when checking the completion or suspension status of an automatic program / erase operation by reading different sector data within the same bank, be sure to either clo ck the ce or change the address before reading the data. if the ce is fixed to v il or data is read from the same address without the address being changed, the output data may not be output correctly. i/o 7 : data polling data polling is a function to determine the status of automatic program / erase is currently being performed by using i/o 7 . data polling is valid from the rise of the last we in the program / erase command sequence. the status of automatic program is currently being executed can be determined by reading from the program destination addresses. while automatic programming is being executed or while automatic programming is being executed during erasure suspension, the complement of the final data programmed will be output to i/o 7 . upon completion of automatic program, the true value of the programmed data, not the complement, is output. the status of automatic erase is in progress can be determined by reading from the addresses of the sector being erased. if erase is in progress, "0" is output to i/o 7 . if the automatic erase operation is complete or if it is suspend, "1" will be output to i/o 7 when a sector for which erasure is suspended is read. during automatic erase, if all the selected sectors are protected, data polling is valid for approximately 400 m s. the device is then reset to the read mode. if the selected sectors include protected and unprotected sectors, only unprotected sectors are erased, and protected sectors are ig nored. upon completion of automatic program / erase, after the data output to i/o 7 changes from the complement to the true value, i/o 7 changes asynchronously like i/o 0 to i/o 6 while oe is maintained at low level. for the timing wavefor m and flow chart, refer to timing waveform for data polling and figure 6. i/o 6 : toggle bit the toggle bit is a function that uses i/o 6 to determine the status of automatic program / erase is in progress. the toggle bit is valid from the rise of the last we in the program / erase command sequence. if a continuous read is performed from any address of a bank that is undergoing automatic program or erase, i/o 6 will be toggled. if a sector other than the erased sector is read after auto matic program / erase is complete or when i t is suspended, the i/o 6 toggle operation is stopped, and valid data for the read is output. if a sector for which erasure is suspended is read, ?1? will be output to i/o 6 . continuous read control is performed wit h the oe or ce . if program is performed for an address inside a protected sector, i/o 6 is toggled approximately 1 m s, and then the device is reset to the read mode. moreover, if all the sectors selected at the time of automatic erase are protected, i/o 6 is toggled approximately 400 m s, and then the device is reset to the read mode. in this way, by using i/o 6 , it is possible to determine the status of automatic erase is in progress (or suspended), but to determine whi ch sector is being erased, i/o 2 (toggle bit ii) is used. see section ?i/o 2 (toggle bit ii)?. for the timing waveform and flow chart, refer to timing waveform for toggle bit , timing waveform for i/o 2 vs. i/o 6 and figure 7. i/o 7 =data? start read (i/o 0 to i/o 7 ) an=valid address i/o 7 =data? fail no read (i/o 0 to i/o 7 ) an=valid address i/o 5 =1? yes no pass yes yes figure 6. data polling flow chart no
a29l323 series preliminary (may, 2002, version 0.0) 27 amic technology, inc. i /o 2 : toggle bit ii toggle bit ii is a function that determines the status of automatic erase (or erase suspend) is in progress for a particular sector by using i/o 2 . i/o 2 is toggled when continuous read is performed from addresses in a sector during autom atic erase (or erase suspend). either oe or ce is used to control continuous read. when program to a sector that is not subject to erase suspend is attempted during erase suspend, read from sectors that are not su bject to erase suspend cannot be performed until program is completed. in this case, "1" will be output to i/o 2 if a continuous read is performed from an address in a sector other than an erased sector. in this way, it is possible to determine the status of automatic erase (including erase suspend) is in progress for sectors specified using i/o 2 , but whether the state is erase in progress or erase suspend cannot be determined with i/o 2 . to determine this, i/o 6 (toggle bit) must be used. see section ?i/o 6 (toggle bit)?. for the timing waveform, refer to timing waveform for i/o 2 vs. i/o 6 . i/o5 : exceeding timing limits if the program / erase time exceeds the prescribed number of pulses during automatic program / erase (exceeding timing limit), "1" is out put to i/o 5 and automatic program / erase failure is indicated. moreover, if overwriting "0" to "1" is attempted, the device judges data overwrite to be impossible, and "1" is output to i/o 5 when the timing limit is exceeded. when this happens, execute com mand reset. i/o3 : sector erase timer a 50 m s timeout period occurs following write with the sector erase command sequence before automatic erase starts. during this timeout period, "0" is output to i/o 3 . when automatic erase starts upon completion of the t imeout period, "1" is output to i/o 3 . if sector erase is performed, first confirm whether the device has received a command by using i/o 7 (data polling) or i/o 6 (toggle bit). then, using i/o 3 , check whether automatic erase has started. if i/o 3 is "0", the timeout period is not over, and so it is possible to add sectors to erase. if i/o 3 is "1", automatic erase starts and other commands (except erase suspend) are ignored until erase is completed. if a sector to erase is added during the sector erase timeout period, it is recommended to check i/o 3 prior to and following the addition. if i/o 3 is "1" following the addition, that addition may not be accepted. ry by : read/ busy the ry/ by is a dedicated output pin used to check the status of automatic program / erase is in progress. during automatic program / erase, "0" is output to the ry / by . if "1" is output, this signifies that the device is either in the read mode (including era se suspend) or standby mode. since the ry/ by is an open - drain output pin, it is possible to connect several ry/ by in series by connecting a pull - up resistor to vcc. for the timing waveform, refer to timing waveform for ry/ by (ready / busy ). i/o 7 =toggle? start read (i/o 0 to i/o 7 ) an=any address in the bank being executed i/o 7 =toggle? fail no read (i/o 0 to i/o 7 ) an=any address in the bank being executed i/o 5 =1? yes no pass yes no figure 7. toggle bit flow chart no
a29dl323 series preliminary (may, 2002, version 0.0) 28 amic technology, inc. table 9. hardware sequence flags i/o 7 i/o 6 i/o 5 i/o 3 i/o 2 ry/ by status (note 1) (note 2) (note 3) (note 1) program 7 i/o toggle 0 0 1 0 erase 0 toggle 0 1 toggle 0 program sector data data data data data data program suspend other than program sector data data data data data 1 erase suspend sector 1 1 0 0 toggle 1 other than erase s uspend sector data data data data data 1 progress erase suspend erase suspend program 7 i/o toggle 0 0 1 0 program 0 toggle 1 0 1 0 erase 0 toggle 1 1 n/a 0 exceeding time limits erase suspend erase suspend program 7 i/o toggle 1 0 n/a 0 notes: 1. to read i/o 7 or i/o 2 , a valid address must be input. 2. to read i/o 6 , any address can be used. 3. for i/o 5 , ?1? is output if the automatic program / erase time exceeds the prescribed number of internal pulses.
a29dl323 series preliminary (may, 2002, version 0.0) 29 amic technology, inc. electrical characteristics before turni ng on power, input gnd 0.2 v to the reset pin until vcc vcc (min.). dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test description min. typ. max. unit high level input voltage v ih 2.4 vcc+0.3 v low level input voltage v il - 0.3 +0.5 v high l evel output voltage v oh i oh = - 500 a, vcc = vcc (min.) 2.4 v low level output voltage v ol i ol = +1.0 ma, vcc = vcc (min.) 0.4 v input leakage current i li - 1.0 +1.0 a output leakage current i lo - 1.0 +1.0 a t cycle = 5 mhz 10 16 byte mode t cycle = 1 mhz 2 4 t cycle = 5 mhz 10 16 read word mode i cc1 vcc = vcc (max.), ce = v il , oe = v ih t cycle = 1 mhz 2 4 ma program, erase i cc2 vcc = vcc (max.), ce = v il , oe = v ih 15 30 ma standby i cc3 vcc = vcc (max.), ce = reset = wp (acc) = vcc 0.3 v, oe = v il 0.2 5 a standby / reset i cc4 vcc = vc c (max.), reset = gnd 0.2 v 0.2 5 a automatic sleep mode i cc5 v ih = vcc 0.2 v, v il = gnd 0.2 v 0.2 5 a read during programming i cc6 v ih = vcc 0.2 v, v il = gnd 0.2 v 21 45 ma read during erasing i cc7 v ih = vcc 0.2 v, v il = gnd 0.2 v 21 45 ma programming during suspend i cc8 ce = v il , oe = v ih , automatic programming during suspend 17 35 ma wp (acc) pin 5 10 power supply current accelerated programming i acc vcc 15 30 ma reset high level input voltage v id high voltage is applied 11.5 12.5 v accelerated programming voltage v acc high voltage is applied 8.5 9.5 v low vcc lock - out voltage (note) v lko v ih = vcc 0.3v ; v il = vss 0.3v 1.7 v no tes: 1. when vcc is equal to or lower than v lko , the device ignores all write cycles. remark: these dc characteristics are in common regardless of product classification.
a29l323 series preliminary (may, 2002, version 0.0) 30 amic technology, inc. ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions input waveform (rise and fall time 5 ns) 3.0v 0v 1.5v 1.5v test points output waveform 1.5v 1.5v test points output load 1 ttl + 30pf read cycle parameter symbol test condition min. typ. max. unit notes read cycle time t rc 85 ns address access time t acc ce = oe = v il 85 ns ce access time t ce oe = v il 85 ns oe access time t oe ce = v il 40 ns output disable time t df oe = v il or ce = v il 30 ns output hold time t oh 0 ns reset pulse width t rp 500 ns reset hold time before read t rh 50 ns reset low to read mode t ready 20 m s ce low to /byte low, high t elfl /t elfh 5 ns byte low output disable time t flqz 30 ns byte high access time t fhqv 85 ns remark: t df is the time from inactivation of ce or oe to hi - z state output.
a29dl323 series preliminary (may, 2002, version 0.0) 31 amic technology, inc. ac characteristics write cycle (program / erase) parameter symbol min. typ. max. unit notes write cycle time t wc 85 ns address setup time ( we to address) t ac 0 ns addres s setup time ( ce to address) t as 0 ns address hold time ( we to address) t ah 45 ns address hold time ( ce to address) t ah 45 ns input data setup time t ds 35 ns input data hold tim e t dh 0 ns read 0 oe hold time toggle bit, data polling t oeh 10 ns read recovery time before write ( oe to ce ) t ghel 0 ns read recovery time before write ( oe to we ) t ghwl 0 ns we setup time ( ce to we ) t ws 0 ns ce setup time ( we to ce ) t cs 0 ns we hold time ( ce to we ) t wh 0 ns ce hold time ( we to ce ) t ch 0 ns write pulse width t wp 35 ns ce pulse w idth t cp 35 ns write pulse width high t wph 30 ns ce pulse width high t cph 30 ns byte programming operation time t bpg 9 200 m s word programming operation time t wpg 11 200 m s sector erase operation time t ser 0.7 5 s 1 vcc set time t vcs 50 m s ry/ by recovery time t rb 0 ns reset pulse width t rp 500 ns reset high - voltage (v id ) hold time from high of ry/ by when sector group is temporar ily unprotect t rrb 20 m s reset hold time t rh 50 ns from completion of automatic program / erase to data output time t eoe 85 ns ry/ by delay time from valid program or erase operation t busy 90 ns address setup time to oe low in toggle bit t aso 15 ns address hold time to ce or oe high in toggle bit t aht 0 ns
a29dl323 series preliminary (may, 2002, version 0.0) 32 amic technology, inc. write cycle (program / erase) (continued) parameter symbol min. typ. max. u nit notes ce pulse width high for toggle bit t ceph 20 ns oe pulse width high for toggle bit t oeph 20 ns voltage transition time t vlht 4 m s 2 rise time to v id ( reset ) t vidr 500 ns 3 rise time to v acc ( we (acc )) t vaccr 500 ns 2 erase timeout time t tow 50 m s 4 erase suspend transition time t spd 20 m s 4 notes: 1. the preprogramming time prior to the erase operation is not included. 2. sector group protection and a ccelerated mode only. 3. sector group protection only. 4. table only. write operation (erase / program) performance parameter description min. typ. max. unit sector erase time excludes programming time prior to erasure 0.7 5 s chip erase time excludes progra mming time prior to erasure 50 s byte programming time excludes system - level overhead 9 200 m s word programming time excludes system - level overhead 11 200 m s byte mode 40 chip programming time excludes system - level overhead word mode 25 s a ccelerated programming time excludes system - level overhead 7 150 m s erase / program cycle 1,000,000 cycle
a29dl323 series preliminary (may, 2002, version 0.0) 33 amic technology, inc. timing waveform for read cycle (1) addresses (input) addresses stable ce (input) oe (input) we (input) data out high-z i/o (output) t rc t oeh t oe t ce high-z t oh t df t acc timing waveform for read cycle (2) addresses (input) addresses stable ce (input) oe (input) data out high-z i/o (output) t rc t rp high-z t oh t acc t rh t ready t ce
a29dl323 series preliminary (may, 2002, version 0.0) 34 amic technology, inc. timing wa veform for sector group protection v id v ih reset (input) address (input) vcc t vcs t vidr sgax sgax sgay t oe t wp timeout t wc t vlht t wc a0 (input) a1 (input) a6 (input) ce (input) oe (input) we (input) i/o (input / outpu) 60h 60h 40h 01h (note) 60h note: the sector group protection verification result is output 01h: the sector group is protected. 00h: the sector group is not protected
a29dl323 series preliminary (may, 2002, version 0.0) 35 amic technology, inc. timing waveform for temporary sector group unprotect program or erase command sequence ~ ~ ~ ~ t rrb we (input) ce (input) ry/by (output) ~ ~ v id v ih reset (input) vcc t vcs t vidr t vlht t vlht t vlht period during which protection is canceled timing waveform for accelerated mode program or erase command sequence ~ ~ ~ ~ t rrb ce (input) we (input) ry/by (output) ~ ~ v id v ih reset (input) vcc t vcs t vaccr t vlht t vlht t vlht accelerated mode period ~ ~
a29dl323 series preliminary (may, 2002, version 0.0) 36 amic technology, inc. timing waveform for dual operation address (input) ba1 input ba2 ba1 ba2 ba1 ba2 output input output status output t rc t wc t rc t wc t rc t wc t as t ah t acc t ceph t aht t as t df t df t ce t oe t oeh t wp t ghwl t dh t ds ce (input) oe (input) we (input) i/o (input / outpu) timing waveform for write cycle ( we controlled) addresses (input) ce (input) oe (input) we (input) i/o (input / output) 555h pa d out i/o 7 data polling note : 1. this timing waveform shows the last two write cycles among the program command sequence's four write cycles, and data polling. 2. this timing waveform shows the word mode's case. in the byte mode, address to be input is different from the word mode. see table 8. command sequence. 3. pa : program address pd : program data i/o 7 : the output of the complement of the data written to the device. d out : the output of the data written to the device. t bpg or t wpg t as t wc t wp t cs t wph t dh pa 3rd and 4th write cycle t ah t rc pd a0h d out t ce t oe t oh t ghwl t ch t ds
a29dl323 series preliminary (may, 2002, version 0.0) 37 amic technology, inc. timing waveform for write cycle ( ce controlled) addresses (input) ce (input) oe (input) we (input) i/o (input / output) 555h pa d out i/o 7 data polling note : 1. this timing waveform shows the last two write cycles among the program command sequence's four write cycles, and data polling. 2. this timing waveform shows the word mode's case. in the byte mode, address to be input is different from the word mode. see table 8. command sequence. 3. pa : program address pd : program data i/o 7 : the output of the complement of the data written to the device. d out : the output of the data written to the device. t bpg or t wpg t as t wc t wh pa 3rd and 4th write cycle t ah t rc pd a0h d out t ce t oe t oh t ghwl t ds t cp t cph t ws t dh
a29dl323 series preliminary (may, 2002, version 0.0) 38 amic technology, inc. timing waveform for sec tor / chip erase address (input) 555h 55h 2aah 555h 555h 2aah fsa (note) aah aah 80h 55h t rc t wc ce (input) i/o (input / outpu) 30h t ah t ch t cs t ghwl t wp t wph t vcs t dh t ds (10h for chip erase) oe (input) we (input) vcc note : 1. fsa is the sector address to be erased. in the case of chip erase, input 555h (word mode), aaah (byte mode). 2. this timing chart shows the word mode's case. in the byte mode, address to be input is different from the word mode. see table 8. command sequence.
a29dl323 series preliminary (may, 2002, version 0.0) 39 amic technology, inc. timing waveform for data polling i/o 7 status data t df valid data d out (note) t oe t ce t oeh t ch t busy t bpg, t wpg, t ser t eoe hi-z hi-z ce (input) oe (input) we (input) i/o 0 -i/o 6 (output) ry/by (output) i/o 7 (output) note : 1. i/o 7 = d out : true value of program data (indicates completion of automatic program / erase)
a29dl323 series preliminary (may, 2002, version 0.0) 40 amic technology, inc. timing waveform for toggle bit va toggle toggle toggle stop toggle (note) valid data out input data t busy t oe t dh t oeh t oeph t aso t aht t as t aht t ceph t ce t oeh addresses (input) ce (input) we (input) oe (input) i/o 6 , i/o 2 (input / output) ryby (output) note : 1. i/o 6 stops the toggle (indicates automatic program / erase completion). timing waveforms for i/o 2 vs. i/o 6 input of automatic erase command erase suspended erase suspended input of program command erase resumed we (input) i/o 6 (output) i/o 2 (output) erasure erase suspend read erase suspend read erasure completion of erasure toggle i/o 2 and i/o 6 (ce or oe is used for toggle) ~ ~ ~ ~ ~ ~ erase suspend input of program command ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
a29dl323 series preliminary (may, 2002, version 0.0) 41 amic technology, inc. timing waveform for ry/ by (read / busy) ~ ~ t busy rising edge of the last write pulse automatic program or erase ce (input) we (input) ry/by (output) timing waveform for reset / ry / by t rpd t rb we (input) reset (input) ry/by (output) t rp timing waveform for byte input determined failing edge of last write pulse t ah t as oe, we (input) byte (input)
a29dl323 series preliminary (may, 2002, version 0.0) 42 amic technology, inc. timing waveform for b yte mode switching data output i/o 0 to i/o 14 data output i/o 0 to i/o 7 t elfl hi-z ce (input) byte (input) i/o 1 5 (output), a-1(input) i/o 0 to i/o 14 (output) data output i/o 15 address input a-1 hi-z hi-z t acc t flqz timing waveform for word mode switching data output i/o 0 to i/o 7 t elfh hi-z ce (input) byte (input) i/o 1 5 (output), a-1(input) i/o 0 to i/o 14 (output) hi-z t fhqv data output i/o 0 to i/o 14 data output i/o 15 address input a-1 hi-z t ce
a29dl323 series preliminary (may, 2002, version 0.0) 43 amic technology, inc. latch - up characteristics description min. max. input voltage with respect to vss on all i/o pins - 1.0v vcc+1.0v vcc current - 100 ma +100 ma input voltage with respect to vss on all pins except i/o pins (including a9, oe and reset ) - 1.0v 12.5v includes all pins except vcc. test conditions: vcc = 5.0v, one pin at time. capacitance (t a = 25 c, f = 1mhz) parameter symbol parameter description test setup typ. max. unit c in input capacitance v in =0 6 7.5 pf c out output capacitance v out =0 8.5 12 pf notes: 1. v in : input voltage, v out : output voltage 2. these parameters are not 100% tested. data retention parameter test conditions min unit 150 c 10 years minimum pattern data retention time 125 c 20 years
a29dl323 series preliminary (may, 2002, version 0.0) 44 amic technology, inc. ordering information part no. access time (ns) operating supply voltage (v) boot sector package a29dl323tv - 90 top ad dress (sector) (t type) 48pin tsop a29dl323uv - 90 bottom address (sector) (b type) 48pin tsop a29dl323tg - 90 top address (sector) (t type) 63 - ball tfbga a29dl323ug - 90 90 2.7 to 3.6 bottom address (sector) (b type) 63 - ball tfbga
a29dl323 series preliminary (may, 2002, version 0.0) 45 amic technology, inc. package information tsop 48l (t ype i) outline dimensions unit: inches/mm 1 e c d l q detail "a" 0.25 24 25 48 d 1 d y e s a 1 a 2 a detail "a" b dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.037 0.039 0.042 0.94 1.00 1.06 b 0.007 0.009 0.011 0.18 0.22 0.27 c 0.004 - 0.008 0.12 - 0.20 d 0.779 0.787 0.795 19.80 20.00 20.20 d 1 0.720 0.724 0.728 18.30 18.40 18.50 e - 0.472 0.476 - 12.00 12.10 e 0.020 basic 0.50 basic l 0.016 0.020 0.024 0.40 0.50 0.60 s 0.011 typ. 0.28 typ. y - - 0.004 - - 0.10 q 0 - 8 0 - 8 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension s includes end flash.
a29dl323 series preliminary (may, 2002, version 0.0) 46 amic technology, inc. package information 63 balls tfbga (7 x 11mm) outline dimensions unit: mm 0.05 11.00 8 7 6 5 4 3 2 1 a b c d e f g h j k l m 4 5.6 0.7 8.8 0.8 1.1 7.00 0.05 ball#a1 corner a 0.10 c m 0.05 m b c 0.35 a b ball*a1 corner top view bottom view side view c seating plane // 0.1 c 1.2 max. 0.05 0.25 0.08 c

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